1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
Conventionally, in order to increase speed and capacity in a semiconductor package, there is an example of stacking a number of memory elements in layers in one package, an example of loading a memory element and a logic element together in one package, or the like.
For example, JP 2005-244143 describes a semiconductor device in which a number of semiconductor memories are mounted on the top surface of a resin interposer (corresponding to a package substrate), and in which an interface chip is stacked on its top layer with a through electrode with a short wiring distance.
Further, “Wide band/large-capacity-memory-loaded SMAFTI package technique” (NEC Technical Journal vol. 59, No. 5/2006, pp. 46-49) describes a general-purpose LSI package in which a micro wiring body (corresponding to a package substrate) called an FTI (Feedthrough Interposer) is inserted between a logic chip and a large-capacity memory chip.
In a semiconductor package, in the case in which the heating value of a semiconductor element is higher than an allowable value, a radiator is mounted on the package in order to suppress a rise in the temperature of the semiconductor element. Therefore, a technique of reducing the thermal resistance between the radiator and the semiconductor element is required.
For example, JP 2005-244143 describes the configuration in which an interface chip with a large heating value is mounted on the uppermost layer near a radiator plate.
Further, JP 9-260554 describes a semiconductor package in which a heat transfer plate having high thermal conductivity is provided between the undersurface of a semiconductor element and a mounting substrate.
JP 9-293808 describes the configuration in which a metallic heat release fin is mounted on the back surface of the semiconductor element exposed on the top surface of a package, via an adhesive.
Recently, a liquid-cooling method which makes noise reduction and high heat radiating performance compatible has been put to practical use. For example, FIG. 2 of “Water-cooling technique for hot devices, Aiming at popularization by standardization and downsizing” (Nikkei Electronics, 2003. 7.21, pp. 59-68) illustrates an example of practical use in which heat is transported to the heat radiating section disposed at a distant position from the heat receiving section disposed on a microprocessor. A water-cooling module includes a heat receiving section (also called a heat absorbing section), a reservoir tank, a heat radiating section (also called a heat exchanger), a pump and a pipe connecting them, as main components.
Further, there is an example of using a sheet, in order to downsize the component of liquid cooling. For example, JP 2001-237582 describes the configuration in which a heat radiating section is formed into a bag shape by a flexible sheet having high heat resistance and high thermal conductivity. JP 2007-10277 describes the configuration in which a heat radiator and a heat absorber are formed by bags made of a water-resistant sheet.
As the best liquid-cooling method, there is an example of the development of a cooling module with high efficiency that uses a fine micro-channel of 200 μm or less. For example, FIG. 7 of “Water-cooling technique for hot devices, Aiming at popularization by standardization and downsizing” illustrates a configuration in which a micro-channel/heat sink is mounted on the upper portion of the microprocessor via grease. The micro-channel/heat sink is configured by forming a trench having a width of 150 μm or less and a depth of 200 μm in a thin plate of silicone by an MEMS technique.
Further, in a case of a package in which chips are stacked in layers, there is also an example of cooling individual chips in the package. For example, JP 2005-5529 describes the method for liquid-cooling the inside of a package by using a hollow portion formed by stacking semiconductor elements via bumps as a channel.
In order to obtain high speed transmission performance with a stacked memory by a through electrode, the interface chip is desirably disposed in a lower layer instead of an upper layer of the stacked memory. Because, in the case in which the interface chip which controls signal distribution is on the upper layer of the stacked memory, if the stacked memory becomes thicker, the transmission path will become longer, and therefore, a signal received from the solder ball, which is the input and output terminal of the package, would be delayed.
As described in “Wide band/large-capacity-memory-loaded SMAFTI package technique”, a logic chip on the undersurface of a package substrate is advantageous with respect to signal transmission. However, when the heating value of the logic chip becomes large, space for mounting the fin described in JP 9-293808, and the water-cooling jacket illustrated in FIG. 2 of “Water-cooling technique for hot devices, Aiming at popularization by standardization and downsizing” cannot be ensured. Meanwhile, as described in JP 9-260554, a heat transfer plate can be provided in this space. However, the heat radiating ability of the mounting substrate is too small to cool the logic element that has a large heating value (of tens of watts).
Further, the periphery of a logic chip is surrounded by mounting bumps, and therefore, even if a thin cooling jacket comprising the micro-channel illustrated in FIG. 7 of “Water-cooling technique for hot devices, Aiming at popularization by standardization and downsizing” is mounted, space for receiving a pipe cannot be provided. Meanwhile, the liquid-cooling method in which a refrigerant flows into a space between the chips inside the package is likely to cause corrosion to the circuit surface between the chips and to electrical connection portions of the upper and lower chips.
Accordingly, in a semiconductor device in which a mounting substrate, the semiconductor element and a package substrate are sequentially stacked in layers, a technique for efficiently cooling a semiconductor element is needed.